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MGCM01
TDMA/AMPS Baseband Interface
DS2497
ISSUE 3.3
December 2002
Features
q q q q q q q q q
Ordering Information
MGCM01/KG/TP1N
IS136 TDMA/AMPS Compatible Channel Filtering (30kHz) FM Demodulator RSSI Output Dual IF Synthesisers Flexible Power Control Fully Programmable via Serial Bus 3 Volt operation 48-pin TQFP package
Applications
q Dual Mode TDMA/AMPS Mobile Telephones q Dual Band (PCS1900/900) TDMA/AMPS
The inputs for the receive path are I and Q signals at an IF of 60kHz. The I and Q signals are filtered by a 60kHz switched capacitor bandpass filter and are then demodulated to give baseband I and Q signals. The MGCM01 also provides voltage gain so that the baseband outputs can be input directly to an A to D converter. The internal FM discriminator can be used for demodulating AMPS signals; the receive path also provides RSSI. Transmit I and Q baseband signals from D to A converters can be input directly to the MGCM01, which provides reconstruction filters and a variable gain buffer. The two PLL synthesisers are used for generation of the receive and transmit IF LO signals.
Mobile Telephones
q PCS 1900 TDMA Mobile Telephones
Description
The MGCM01 provides channel filtering for IS136 TDMA/ AMPS mobile telephones.
RECEIVE SECTION
RXI IP1/2
13/14
4/3
RXI OP1/2
ATTENUATOR
S
RXQ IP1/2
15/16
90
60kHz
2/1 10
ATTENUATOR
RXQ OP1/2 AUDIO FB AUDIO RSSI FB RSSI
SCLK SDAT SLATCH RESET PCA
43 39 44 46 45
CONTROL
FM DISCRIMINATOR RSSI
9 11 7
28
TXI IP1/2 TXQ IP1/2
33/32
TX FM TXI OP1/2 TXQ OP1/2
36/35
TRANSMIT SECTION
29/30 26/27
RX VCO UHF LOCK TX VCO
20 25 22
SYNTHESISERS
18
RX PD LOCK DET TX PD
RX LOCK SELECT TX
38
24
Figure 1 - MGCM01 block diagram
MGCM01
GND RSSI FB AUDIO FB AUDIO GND RSSI VDD GND RXI OP1 RXI OP2 RXQ OP1 RXQ OP2
PIN 1 PIN 48
RXI IP1 RXI IP2 RXQ IP1 RXQ IP2 VDD RX PD GND RX VCO GND TX VCO VDD TX PD
MGCM01
RTUNE VBG RESET PCA SLATCH SCLK GND VDD TCXO SDAT LOCKDET GND
UHF LOCK TXQ OP1 TXQ OP2 TX FM TXI OP1 TXI OP2 VDD TXI IP2 TXI IP1 GND TXQ IP2 TXQ IP1
TP48
Figure 2 - Pin connections - top view
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Name RXQ OPRXQ OP+ RXI OPRXI OP+ GND VDD RSSI GND AUDIO AUDIO FB RSSI FB GND RXI IP+ RXI IPRXQ IP+ RXQ IPVDD RX PD GND RX VCO GND TX VCO VDD TX PD
Type O O O O GND PWR O GND O I I GND I I I I PWR O GND I GND I PWR O
Description Baseband receive Q outputBaseband receive Q output+ Baseband receive I outputBaseband receive I output+ Ground (substrate connection) Power - RSSI/demodulator RSSI output Ground - RSSI/demodulator Demodulator audio/data output Demodulator feedback RSSI feedback Ground - receive section Receive I Input+ Receive I InputReceive Q Input+ Receive Q InputPower - receive section Rx PLL charge pump output Ground (substrate connection) Receive IF PLL input Ground - synthesiser Transmit IF PLL input Power - synthesiser Tx PLL charge pump output
Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Name UHF LOCK TXQ OP+ TXQ OPTX FM TXI OP+ TXI OPVDD TXI IPTXI IP+ GND TXQ IPTXQ IP+ GND LOCK DET SDAT TCXO VDD GND SCLK SLATCH PCA RESET VBG RTUNE
Type I O O O O O PWR I I GND I I GND O I I PWR GND I I I I O I
Description UHF synthesiser lock input Transmit Q output+ Transmit Q outputTransmit FM output Transmit I output+ Transmit I outputPower - transmit section Transmit I inputTransmit I input+ Ground TX channel Transmit Q inputTransmit Q input+ Ground (substrate connection) Synthesiser lock detect output Serial interface, serial data in 19*44MHz reference from TCXO Power supply - digital Ground - digital Serial interface clock Serial interface latch Power control assert Chip master reset (active low) Bandgap reference decoupling Bias Ref. - connect 100k to GND
Table 1 Pin descriptions
Absolute Maximum Ratings
Supply voltage (VDD ) Voltage applied to any pin Operating temperature -0*3V to +3*9V -0*3V to V DD +0*3V -30C to +100C Storage temperature Max. junction temperature ESD (Human Body Model) -55C to +150C +150C 2kV
2
MGCM01
Electrical Characteristics
TAMB = -30C to +85C, VDD = 3V 10%, VEE = 0V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristic Supply Current Sleep Power down Receive section (I/Q) Receive section (FM) Receive section (I/Q) Receive section (FM) Transmit section (I/Q) Transmit section (FM) Logic Inputs Input voltage high, VIH Input voltage low, VIL Input current Input capacitance Logic Outputs Output voltage low, VOL Output voltage high, VOH Output current Serial Control Timing SDATA set up time, t1 SDATA hold time, t2 SCLK pulse width t3 SLATCH set up time, t4 SLATCH pulse width, t5 SCLK period, t6 Switch on/off times TX turn on/turn off time RX turn on/turn off time TCXO Input Input resistance Input capacitance Input sensitivity Frequency Min. Typ. 20 550 10 9 Max. Units Conditions
100 12*5 12 14 14 8 5*5
5*2 2*8 0*8VDD
A A mA mA mA mA mA mA V V nA pF V V mA
Reference circuits active At 25C and VDD = 3*0V At 25C and VDD = 3*0V
0*2VDD 10 10 0*4 0*6VDD 1 20 20 50 20 50 100 0*5 1*0 10 10 0*5 19*44
VIN = 0V to VDD
See Figure 3 ns ns ns ns ns ns ms ms k pF Vp-p MHz
2
AC coupled cont...
t1 SLCK
t3
t2 SDATA BIT 23 BIT 22
t6 BIT 21 BIT 0
t4 SLATCH
t5
Figure 3 - Serial bus timing diagram
3
MGCM01
Electrical Characteristics (continued)
Value Characteristic Receive - General Input impedance Output impedance Input voltage RXI, RXQ Output voltage RXI, RXQ Out of band 60kHz 1dB compression Out of Band 120 kHz 1dB compression Input IP3 Receive (I/Q Mode) Input signal Gain I/Q gain matching I/Q quadrature accuracy l/Q bandwidth Matching Group delay ripple Gain ripple Noise Output 1dB compression LO breakthrough Other spurious signals Receive (FM Mode) Input signal Audio output Receive Filter (Bandpass) Centre frequency 3dB bandwidth Stop band attenuation 0 to 3kHz 3 kHz to 10kHz 10 kHz to 22kHz 38kHz 82kHz 98kHz to 110kHz 110kHz to 117kHz 117kHz to 123kHz 123kHz to 1*36MHz 1*36MHz to 1*52MHz 1*52MHz to 10MHz Image attenuation 0 to -10kHz -10kHz to -42kHz -42kHz to -78kHz -78kHz to -105kHz -105kHz to -1*36MHz -1*36MHz to -1*52MHz -1*52M Hz to -10MHz Gain Ripple Min. Typ. Max. Units Conditions
10 2 VDD/2 VDD-1*6 VDD -1*4 VDD-1*2 125 13 0*65 1*0 0*53 56 TBD 0*5 14 1*5 3 10 22 -4 0
k k V V mV mV V mV dB dB deg % s p-p dB p-p V V p-p mV dB V mV kHz kHz dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
Differential Differential Input normally AC coupled Note 2 Note 2 Note 3 Differential (gain = 56dB) See Table 6
54 -0*5
58*5 0*5 TBD 2 16 2*2 17
0 to 12*5kHz 0 to 12*5kHz 10Hz to 100kHz referred to input Differential 60kHz
30 500 60 16 67 61 48 18 18 48 61 68 71 36 71 61 40 25 40 61 36 61 69 63 51 20 20 50 63 70 73 48 73 18
Output SINAD = 12dB Defined by external components Note 4 Figure 5 Relative to signal at 60kHz
Note 5 Note 5
Figure 6
28
48 1*0 1*5
cont...
4
MGCM01
Electrical Characteristics (continued)
Value Characteristic RSSI Dynamic range Accuracy RSSI slope Input signal Input signal RSSI output level Attenuator gain Attenuator switch-in level Attenuator switch-out level RSSI output impedance Transmit (I/Q and FM) Gain Min. 70 -3 17 0*024 0*024 VDD /2-1*2 -31*5 Typ. 73 20 Max. Units Conditions
-32*5 4*5 2*25 1 12 9 6 3 0 0*8 1*2
dB dB +3 mV/dB 23 mV 110 mV 20 V VDD/2+1*2 dB -33*5 mV mV k 13 9*5 6*5 3*5 0*5 1*4 2 2 +0*3 0*7 30 29 1 10 dB dB dB dB dB V V Vp-p Vp-p dB deg mVp-p kHz dB s dB dB dBc dBc dBc dBc MHz mV A A A A V
Internal attenuator enabled Internal attenuator disabled
Input referred Input referred
11 8*5 5*5 2*5 -0*5 1*0
See Table 9 See Table 9 See Table 9 See Table 9 See Table 9
Input DC voltage Output DC voltage Input signal range Output signal range Output amplitude balance Output phase balance Output DC offset 3dB filter bandwidth Gain ripple Group delay variation Stop band attenuation Noise, in band Noise 20 to 45kHz Noise 45 to 60 kHz Noise >= 60 kHz Synthesisers Input frequency Input sensitivity Charge pump current, IO
Note 6 Note 6
-0*3 20 25
22
30 40 - 50 - 60 - 75 - 85 1 100 400 140 75 13 0*5 115 496 176 96 16 600 210 115 19 VDD-0*5
0 to 12*5kHz 0 to 12*5kHz 100kHz to 2 MHz >2MHz Note 7 BW = 300Hz BW = 300Hz BW = 300Hz
Charge pump output compliance
Default mode, see Table 12 See Table 12 See Table 12 See Table 12 IO 15%
NOTES 1. All signal voltages are RMS unless stated otherwise. 2. Level of out of band blocking signal to cause 1dB compression of in band wanted signal. 3. Measured with unmodulated blocking signals at 60 and 120kHz. 4. These filter characteristics are for the 60kHz bandpass filter. This provides all the filtering in FM mode. There is additional filtering in l/Q mode provided by the baseband low pass filters. Details are shown in Figure 4. 5. Extrapolate linearly between 22kHz-38kHz, 82kHz-98kHz. 6. The input and output signal ranges are the maximum available. For example if the input signal is 2V pk-pk then the programmed gain must only be 0dB. 7. Noise relative to full scale signal.
5
MGCM01
OPERATING DESCRIPTION Receive
TDMA IS136 mode The receive path filtering is shown in more detail in Figure 4. The inputs to the MGCM01 are I and Q signals at an IF of 60 kHz. These can be generated by a quadrature demodulator circuit such as the Zarlink Semiconductor MGCR01 (Saturn) AGC amplifier and demodulator. This device is normally used for mixing direct to baseband but can also mix down to low IF quadrature signals. The I and Q signals are passed through anti-alias filters to prevent spurious responses in the subsequent switched capacitor filter. The anti-alias filter is a third order Butterworth with a 230kHz cutoff. The I and Q signals are then combined and passed through a switched capacitor bandpass filter. This filter is a tenth order Chebychev. The advantage of using a switched capacitor filter is that it gives very stable performance and no calibration is required. The circuit also provides rejection of the image frequency following the down conversion to 60kHz. Following the bandpass filter the signal is mixed down to baseband I and Q and is output from differential outputs. There is additional baseband filtering to remove spurious signals from the down converters and clock breakthrough from the switched capacitor filters. Further detail of the filtering in the the MGCM01 receive path is shown in Figure 4. The baseband outputs can be fed directly into A to D converters in a baseband circuit. AMPS FM Mode Demodulation can be performed using the I and Q baseband signals. However, the MGCM01 also includes a limiting amplifier and an FM discriminator. The FM discriminator consists of a shift register acting as a delay line. The output of the discriminator is a digital signal which must be filtered to recover the audio signal. The discriminator output is routed through the cascaded baseband I and Q low pass smoothing filters and finally through an output buffer stage. External components can be used to optimise the gain and frequency response of the output amplifier. Further information on using MGCM01 in FM mode is provided in application note "MGCM01 in AMPS environment". RSSI The MGCM01 also contains RSSI circuitry. This would normally be used when using the FM discriminator to provide the received signal strength to the phone's microcontroller. The RSSI circuit has over 70dB dynamic range. In the presence of strong signals the RSSI circuit switches in a 32dB attenuator in the IF I and Q input stages to optimise dynamic range. The RSSI circuit will not normally be used in I/Q mode except if required to monitor base station signal strength. A block diagram of the RSSI circuit is shown in Figure 7. The switched capacitor filter has a limited dynamic range of approximately 50dB due to aliased noise from the sampling process used. In order to enable the RSSI to operate over a larger dynamic range the RSSI output is input to a comparator. The output of the comparator then switches a 32*5dB attenuator in the 60kHz I and Q input stages and enables a larger dynamic range for the RSSI. Hysteresis is built in to prevent oscillation when close to the threshold level. Figure 8 shows the RSSI characteristic. At low signal levels the RSSI output increases with signal level; however, at high signal level when the attenuator is switched in the input path, the RSSI output is mirrored around VDD/2 and decreases with increasing signal level. The slope is the same at high level as at low level but is, of course, negative. The actual slope (or gain) and settling time for the RSSI are set by external components as shown in Figure 7. The RSSI output from the MGCM01 will normally be input into an A to D converter. This, together with the baseband controller can convert the RSSI signal to a monotonic digital output as required by the IS136 specifications. Calibration will be required to determine the slope and offset at low and high signal levels, and the threshold level of the RSSI characteristic. For example if the RSSI output is less than VDD/2 then the RSSI slope is positive; if greater than VDD/2 then the RSSI slope is negative.
I
ANTI-ALIAS LOWPASS BANDPASS SWITCHED CAPACITOR 60kHz CHEBYCHEV n=3 BW = 230kHz n = 10 BW = 660kHz CHEBYCHEV n=3 BW = 37*5kHz BUTTERWORTH n=3 BW = 60kHz LOWPASS SWITCHED CAPACITOR SMOOTHING FILTER LOWPASS
I
60kHz
BUTTERWORTH
Q
Q
TO FM DISCRIMINATOR AND RSSI
Figure 4 - Receive path filters
6
MGCM01
0
20 ATTENUATION (dB)
40
60
80
100
0
30
60
90
120
150
FREQUENCY (kHz)
Figure 5a - Filter response
0
5 ATTENUATION (dB)
10
15
20
25 30 40 50 60 70 FREQUENCY (kHz) 80 90
Figure 5b Passband detail Figure 5 - Bandpass filter response
7
MGCM01
0
20
ATTENUATION (dB)
40
60
80
100
120
0
30
60
90
120
150
FREQUENCY (kHz)
Figure 6 - Bandpass filter image response
27k EXTERNAL COMPONENTS RSSI FB
11
RSSI
1*4n
7
I 60kHz Q
ATT. 32*5dB
ANTI-ALIAS AND BANDPASS FILTERS
RSSI DETECTOR
ATT. 32*5dB RSSI STATE MACHINE
VTH
Figure 7 - RSSI block diagram
RSSI OUTPUT (V)
VDD 2
INPUT SIGNAL (dBm)
Figure 8 - RSSI characteristic
8
MGCM01
TRANSMIT TDMA IS136 Mode I/Q Modulation
The inputs to the MGCM01 are derived from baseband D to A converters. These signals are passed through variable gain buffers. The gain of the buffers can be programmed from 0 to 12 dB in 3 dB increments, as shown in Table 9, allowing compatibility with a number of baseband and transmit modulator devices. The buffers are followed by reconstruction filters to remove spurious responses from preceding D to A converters. These filters are third order Butterworth with 25kHz cut off frequency. The filters contain automatic calibration to set the cut off frequency. This can be controlled via the serial programming bus. All inputs and outputs are differential Table 11, followed by an 11-bit programmable counter and 7-bit swallow counter to control the 2-modulus prescaler. The reference divider is a fully programmable 15-bit counter. The reference frequency is a 19*44MHz TCXO. The synthesiser charge pumps can be programmed to four current levels, as shown in Table 12, to drive the appropriate loop filters. The synthesisers also provide lock detect outputs. There is also a UHF LOCK input, pin 25, which can be connected to the system UHF synthesiser and is then gated with MGCM01 lock detect to give a combined output to the baseband controller via LOCK DETECT output, pin 38. This logic can use either the receive or transmit lock detect as selected via the serial bus.
PROGRAMMING
The MGCM01 features very flexible programming via the 3-wire serial bus. Data is clocked in 24-bit words with a latch pulse following the final data bit. The latch input must be held low at all other times. The serial bus not only programs the modes of operation but also enables unused sections of the chip to be powered on and off as required. This is particularly important in a TDMA system when the phone does not receive or transmit all of the time. An added feature is the PCA (Power Control Assert), pin 45, which allows the MGCM01 to alternate between receive and transmit modes without reloading cammands via the serial bus and give more accurate timing. Details of the serial bus are shown in Table 4. A total of 8 words can be programmed but some of these are for test purposes only and are not required in normal applications. The programming is described in more detail in the following sections. Serial bus timing is shown in the Electrical Characteritics and Figure 3.
AMPS FM Mode
In this mode the input can be either a single ended or differential signal from a baseband D to A converter. The output is a single ended signal and is used to directly modulate the transmit IF. The signal path is the same as for l/Q mode but with only the I channel active and the Q channel powered down. The l+, Q+ outputs are switched high and the l-, Q- outputs are switched low to set the modulator in the Zarlink Semiconductor MGCT02 (Moon) chip to FM mode.
SYNTHESISERS
Two VHF PLL synthesisers are included for the generation of receive and transmit IF LO signals. The synthesisers are compatible with the VCO and prescaler circuits on the Zarlink Semiconductor MGCT02 and MGCR01 devices. The two synthesisers are identical. The synthesisers include 2-modulus prescalers with programmable division ratio from 8/9 to 128/129, as detailed in
9
MGCM01
Word 1 2 3 4 5 6 7 8 X RXDIV<17:0> TXDIV<17:0> REFRX<14:0> REFTX<14:0> RCP, TCP<1:0> RTC, TTC RPR, TPR<2:0> RPP, TPP TLI, RLI LDC TX<1:0> PCS<2:0> RX TXG<2:0> RSS CONT<3:0> TXC TC<3:0> CALCO<7:0> Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 X X X X X X X X X X X X X X X X X X 0 0 TLI RLI 0 TPP 0 X 0 TPR<2:0> X X X RPR<2:0> 0 X RXDIV<17:0> TXDIV<17:0> REFRX<14:0> REFTX<14:0> TTC RTC TCP<1:0> RCP<1:0> LDC 0 TXC TX<1:0> X X TC<3:0> X 0 X X X X X 0 9 8 7 6 5 4 3 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1
X RPP 0 X X X 0 X 0
TXG<2:0> X RSS RX TEST
PCS<2:0>
CONT<3:0>
CALCO<7:0>
Table 4 Serial bus details
Not used Receive synthesiser (LO2) division ratio Transmit synthesiser division ratio Receive synthesiser reference division ratio Transmit synthesiser reference division ratio Receive/Transmit synthesiser charge pump current control Receive/Transmit synthesiser charge pump tristate control Receive/Transmit synthesiser prescaler ratio Receive/Transmit synthesiser phase detector polarity Receive/Transmit lock detect invert Lock detect select Transmit control Power Control system Receive mode Transmit gain RSSI control Receive control Transmit calibrate Transmit calibrate control - set to 1000 Sets transmit cut off frequency - set to 00001100 for standard 25kHz cutoff
Receive Programming
The MGCM01 has two basic receive modes: 1. I/Q mode. The 60 kHz IF signal is mixed down to baseband I and Q signals. This mode is used for IS136 TDMA and may also be used for AMPS. 2. FM mode. The baseband l/Q path is powered down and the MGCM01 discriminator is used for demodulation. This mode can be used for AMPS. These modes are selected by the RX mode bit, Word 7, Bit 11 as shown in Table 5. RX 0 1
Table 5
Additional control is provided by the receive control bits, Word 7 Bits 9:6 (CONT<3:0>). CONT<2> sets the bandwidth of the 60 kHz bandpass filter. The low bandwidth mode (CONT<2> = 1 ) should be used for FM mode. However, the higher bandwidth mode (20 kHz) may be used in TDMA operation. The input attenuator control CONT<3> is active with RSS set to 1 and inactive if RSS is set to 0, as described in the next section. CONT<3:0> X X X 0 1 X 0 1 X X 0 X X X X 0 X X X X
Table 6
Mode 56dB gain (default) 20kHz bandwidth 16kHz bandwidth Attenuator enabled Attenuator disabled
Mode I/Q FM
10
MGCM01
RSS Word 7 Bit 12 allows manual control of the input attenuator in conjunction with CONT<3>.
Synthesiser Programming
The receive and transmit synthesisers are of a similar design and use identical programming. Each synthesiser includes a dual modulus (N, N+1) prescaler followed by A and M counters giving a total division ratio of MN+A, where M is an 11-bit number A is a 7-bit number N is the prescaler modulus; this can also be programmed. The value of A must be less than N.
RSS 0 1
Operation Normal attenuator mode Manual attenuator
Table 7
Transmit Programming
MGCM01 has two basic transmit modes. 1. I/Q mode. I and Q signals from baseband digital to analog converter are filtered and buffered. This mode is used for IS136 TDMA. 2. FM mode. This is used for direct FM modulation of transmit IF oscillator. These modes are controlled by TX <1:0>, Word 6 Bits 9 to 8, as shown in Table 8. TX<1:0> 0 1 0 0
Table 8
The A and M values are combined to give the RXDIV, TXDIV values in Words 1 and 2.
Receive Synthesiser
The M value is programmed in Word 1 Bits 20 to10; the A value is programmed in Word 1 Bits 9 to 3 The reference divider REFRX, a 15-bit number, is programmed in Word 3 bits 17 to 3. The dual modulus prescaler is programmed by RPR<2:0>, Word 5 Bits 14:12, as shown in Table 10 RPR<2:0> 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1
Table 10
Mode TDMA FM Prescaler ratio 8/9 16/17 32/33 64/65 128/129
A calibration of the transmit filters can be initialised by setting TXC, Word 6 Bit 10 to 1. After calibration the internal register for this bit is reset to 0. The transmit gain can be programmed by TXG<2:0>, Word 6 Bits 13 to 11, as shown in Table 9. TXG<2:0> X 0 0 1 1 X 0 1 0 1 1 0 0 0 0
Table 9
Transmit Synthesiser
The M value is programmed in Word 2 Bits 20 to 10; the A value is programmed in Word 2 Bits 9 to 3. The reference divider REFTX, a 15-bit number, is programmed in Word 4 Bits 17 to 3. The dual modulus prescaler is programmed by TPR<2:0>, Word 5 Bits 17 to 15, as shown in Table 11. TPR<2:0> 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1
Table 11
Gain (dB) 0 3 6 9 12
Transmit Calibration This is initiated by setting TXC, Word 6 Bit 10 high. Calibration takes approximately 0.6ms. In order for the calibration to give the required cutoff, CALCO<7:0> Word 8 Bits 23 to 16, must be set to 00001100. The calibration code is then stored in TC<3:0>, Word 6 Bits 6 to 3 and TXC is reset low. If TC<3:0> is overwritten then a further calibration is required.
Prescaler ratio 8/9 16/17 32/33 64/65 128/129
11
MGCM01
Synthesiser Control
The transmit and receive synthesiser control programming is independent but has the same format. The gating for the total lock detect function is shown in Table 17. The RLI and TLI bits should be set to 0. The combined lock detect output is available on Pin 38. UHF RX/TX LOCK lock lock DET 0 1 1 X 0 1 0 0 1 Mode UHF unlocked UHF locked, TX or RX unlocked All PLLs locked
Table 17
Charge Pump Current
Four charge pump currents for each synthesiser can be programmed using RCP<1:0> and TCP<1:0>, Word 5 Bits 7 to 6 and Bits 9 to 8 respectively, as shown in Table 12. This allows additional flexibility when optimising loop filters and overall synthesiser performance. RCP/TCP<1:0> 0 0 1 1 0 1 0 1
Table 12
Current (A) 496 176 96 16
Power Control
The MGCM01 features flexible power control using the PCS<2:0> Word 7, Bits 17 to 15 (see Table 18), using the serial bus in conjunction with the PCA pin. PCS<2:0> 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 Mode Deep Sleep Sleep TX RX Duplex Alt RX/TX RSSI on RSSI off
Table 18
Charge Pump Output control
The charge pump can be inverted using RPP, Word 5 Bit 20 for the receive synthesiser and TPP, Word 4 Bit 18 for the transmit synthesiser as shown in Table 13. RPP/TPP 0 1
Table 13
Mode Normal Inverted
The charge pump outputs can also be put into a high impedance inactive state using RTC and TTC, word 5 Bits 11 and 10 respectively as shown in Table 14. RTC/TTC 0 1
Table 14
Description of Power Control Modes
Deep Sleep In this mode all circuitry is powered down except the power control circuits. Sleep As deep sleep but voltage reference circuits active.
Mode Normal High impedance RX Receive Channel powered on. Operates in conjunction with RX mode control. TX Transmit Channel powered on. Operates in conjunction with TX mode control. Duplex Receive and Transmit channels active. Alt RX/TX Receive and transmit under control of PCA. Receive on when PCA = 0, Transmit on when PCA = 1 RSSI On RSSI circuitry is activated when receive mode subsequently selected. This mode must be selected if RSSI or FM mode is required before setting RX or Duplex mode. RSSI Off RSSI circuitry off when receive mode selected. These power control modes are activated by the PCA pin. The PCA pin must normally be held high whilst a power control instruction is loaded via the serial bus. The exception is the Alt RX/TX mode which is loaded while PCA is low. The receive and transmit modes can then be toggled with the PCA pin.
Lock Detect Output Polarity
The Lock detect output polarity can be inverted using RLI/ TLI, Word 3 Bits 18 and 19, respectively as shown in Table 15. In normal operation lock detect outputs are high when locked. RLI/TLI 0 1
Table 15
Mode Normal Invert
Lock Detect Output Control
The receive or transmit lock detect output can be selected for gating with the UHF LOCK input using the LDC bit, Word 5 Bit 5, as shown in Table 16. LDC 0 1
Table 16
Mode Rx lock Tx lock
12
MGCM01
Application
The MGCM01 requires a minimal number of external components in a typical application. The TCXO input should be AC coupled using a 10nF capacitor. Internal currents in the device are set by a reference resistor connected from pin 48 to ground. The recommended value for this resistor is 100k. External components on the discriminator and RSSI pins control the output characteristics of these functions. The recommended components are shown in Figures 9 and 10.
9
This oscillator normally operates at twice the required LO frequency: an on-chip prescaler divides the oscillator frequency by 4; the prescaler output is used with the MGCM01 PLL. In TDMA mode the AGC should maintain the MGCM01 input signals at typically 0*5mV. The MGCM01 then provides filtering, amplification and finally quadrature modulation down to baseband I and Q signals, which are directly coupled to baseband analog to digital converters. This mode can also be used for FM if l/Q demodulation is being used. The on-chip limiting amplifier and discriminator can be used for AMPS FM demodulation. In this mode MGCR01 AGC is fixed to give an input to MGCM01 of typically 0*1 mV. The 60 kHz I and Q signals are filtered and then combined and passed through the limiting amplifier and discriminator. The components shown in Figure 9 provide feedback around the audio output amplifier and are effectively a bandpass filter. An RSSI output is also generated: the external components shown in Figure 10 set the slope and response time for the RSSI characteristic. These component values are recommended as they provide optimum response time and hysteresis. In the transmit path modulated I and Q signals from baseband digital to analog converters are buffered and filtered. For TDMA mode these are output as I and Q signals to the quadrature modulator inputs of the MGCT02. This modulates an intermediate frequency which is then up-converted to the required RF transmit frequency. For FM mode a single ended output is provided which can be used to directly modulate the MGCT02 oscillator tank circuit. The transmit IF is generated by an oscillator on Moon with an external tank circuit. For IS136 applications this oscillator normally runs at twice the IF frequency and is divided by 2 to generate the IF. A divide by eight prescaler divides the oscillator frequency and provides an output which together with the transmit synthesiser on the MGCM01 controls the IF.
AUDIO 47p AUDIO FB 100n 13k 130k
DISCRIMINATOR OUTPUT
MGCM01
10
Figure 9 - Discriminator output components
7
RSSI 1*5n RSSI FB 27k
RSSI OUTPUT
MGCM01
11
Figure 10 - RSSI output components
Figure 11 shows The MGCM01 operating in a typical IS136 mobile telephone application. This application uses the MGCR01 IF amplifier with AGC and the MGCT02 quadrature modulator and transmit up converter. These devices are part of Zarlink Semiconductor's Planet chipset. The output from the IF filter is amplified in the MGCR01 IF amplifier which also down-converts to 60kHz differential I and Q signals which are then capacitively coupled to the MGCM01. Gain control for MGCR01 is provided from the baseband controller. MGCR01 includes an oscillator to provide the local oscillator for the quadrature down conversion.
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MGCM01
MATCHING
FROM RF MIXER
MATCHING
IF FILTER 30kHZ BW
MGCR01
CDMA_IF CDMA_IF
IOUT IOUT QOUT QOUT VHF_BUF LOOP FILTER AND TANK
RXI IP1 RXI IP2 RXQ IP1 RXQ IP2 RXVCO RXPD TCXO 19*44MHz VCO
MGCM01
VHF_RES TO UHF SYNTHESISER
MATCHING
900MHz PA
SAW 836MHz
TANK RF900 RF900 VCO_OP IIN MGCT02 IIN QIN RF1900 QIN RF1900 LO1GHz LO2GHz
LOOP FILTER AND TANK
MATCHING
1900MHz PA
SAW 1880MHz
TXFM TXPD TXVCO TXI OP1 TXI OP2 TXQ OP1 TXQ OP2
RXI OP1 RXI OP2 RXQ OP1 RXQ OP2 AUDIO RSSI TXI IP1 TXI IP2 TXQ IP1 TXQ IP2
% %
TO BASEBAND ADCs
FROM BASEBAND DACs
Figure 11 - Typical IS136 application
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For more information about all Zarlink products visit our Web Site at
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Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

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